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ISL8563E
TM
Data Sheet
March 2001
File Number
6002
+/-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, EIA/TIA-562, EIA/TIA-232 Transmitters/Receivers
The Intersil ISL8563E contains 3.0V to 5.5V powered transmitters/receivers which meet ElA/TIA-562 and ElA/TIA-232 specifications, even at VCC = 3.0V. Additionally, they provide 15kV ESD protection (IEC 1000-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-562 pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with a manual powerdown function, reduce the standby supply current to a 1A trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. The ISL8563E is fully compatible with 3.3V only systems, mixed 3.3V and 5.0V systems, and 5.0V only systems. This product features an improved charge pump which delivers 5V transmitter supplies, allowing the use of the ISL8563E in RS-562 and RS-232 applications. RS-562 applications will benefit from the improved noise immunity afforded by the 5V output swing capability. Table 1 summarizes the features of the device represented by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the 3V RS-232 family.
Features
* ESD Protection for RS-562 I/O Pins to 15kV (IEC1000) * Drop in Replacement for MAX563, with Improved Output Voltage (5V) for Enhanced Noise Immunity * Meets EIA/TIA-562, and EIA/TIA-232 Specifications at 3V * Latch-Up Free * On-Chip Voltage Converters Require Only Four External 0.1F Capacitors * Receivers Active in Powerdown * Receiver Hysteresis For Improved Noise Immunity * Guaranteed Minimum Data Rate . . . . . . . . . . . . 250kbps * Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 4V/s * Wide Power Supply Range. . . . . . . . Single +3V to +5.5V * Low Supply Current in Powerdown State . . . . . . . . . . 1A
Applications
* Any System Requiring RS-562/RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Digital Cameras - Bar Code Readers
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN9863, "3V to +5.5V, 250K-1Mbps, RS232 Transmitters/Receivers"
Ordering Information
PART NO. ISL8563ECB ISL8563ECB-T ISL8563ECP ISL8563EIB ISL8563EIB-T TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 18 Ld SOIC Tape and Reel 18 Ld PDIP 18 Ld SOIC Tape and Reel PKG. NO. M18.3 M18.3 E18.3 M18.3 M18.3
Pinout
ISL8563E (PDIP, SOIC) TOP VIEW
EN 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 18 SHDN 17 VCC 16 GND 15 T1OUT 14 R1IN 13 R1OUT 12 T1IN 11 T2IN 10 R2OUT
TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL8563E NO. OF NO. OF Tx. Rx. 2 2 NO. OF MONITOR Rx. (ROUTB) 0 DATA RATE (kbps) 250 Rx. ENABLE FUNCTION? YES READY OUTPUT? NO MANUAL POWERDOWN? YES AUTOMATIC POWERDOWN FUNCTION? NO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001, All Rights Reserved
ISL8563E Pin Descriptions
PIN VCC V+ VGND C1+ C1C2+ C2TIN TOUT RIN ROUT EN SHDN System Power Supply Input (3.0V to 5.5V). Internally Generated Positive Transmitter Supply (+5.5V). Internally Generated Negative Transmitter Supply (-5.5V). Ground Connection. External Capacitor (Voltage Doubler) is connected to this lead. External Capacitor (Voltage Doubler) is connected to this lead. External Capacitor (Voltage Inverter) is connected to this lead. External Capacitor (Voltage Inverter) is connected to this lead. TTL/CMOS Compatible Transmitter Inputs with pull-up resistors. 15kV ESD Protected, RS-562/RS-232 level (nominally 5.5V) transmitter outputs. 15kV ESD Protected, RS-562/RS-232 compatible receiver inputs. TTL/CMOS Level Receiver Outputs. Active Low Receiver Enable Control. Active Low Input which shuts down transmitters and on-board power supply, to place device in low power mode. FUNCTION
Typical Operating Circuit
ISL8563E
+3.3V + 0.1F 2 + 4 5 + 6 C1+ C1C2+ C2VCC T1IN 12 400k VCC 11 13 R1 10 R2OUT 1 EN R2 5k 5k 9 R2IN 400k T2 8 T2OUT 14 R1IN RS-562/232 LEVELS T1 15 V-
17 VCC V+ +
C1 0.1F C2 0.1F
C3 0.1F 3 7 +
C4 0.1F
T1OUT
TTL/CMOS LOGIC LEVELS
T2IN R1OUT
SHDN GND 16
18
VCC
2
ISL8563E
Absolute Maximum Ratings
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, EN, SHDN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) 18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 80 18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75 Moisture Sensitivity (see Technical Brief TB363) All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range ISL8563ECX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ISL8563EIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1F; Unless Otherwise Specified. Typicals are at TA = 25oC TEST CONDITIONS All Transmitter Outputs Loaded with 3k to Ground RL = 3k, CL = 1000pF, One Transmitter Switching and Maintaining 5V Output Swing TIN TIN TIN VCC = 3.0V to 5.0V SHDN = VCC SHDN = GND TEMP (oC) Full Full Full Full Full Full Full Full Full Full VCC = 3.3V VCC = 5.0V VCC = 3.3V VCC = 5.0V VCC = 3.0V to 3.6V IOUT = 3.2mA IOUT = -1.0mA EN = VCC VCC = 3.0V to 5.0V Full Full Full Full Full Full Full Full Full Full Full Full MIN 5.0 250 2.4 300 -25 2.4 2.4 0.1 3 2.4 3.0 TYP 5.4 500 2 0.01 10M 35 1.2 1.5 1.5 1.8 0.5 5 0.05 MAX 0.8 20 1.0 10 60 25 0.6 0.8 1.0 7 0.4 10 0.8 5.5 UNITS V kbps V V A A A mA V V V V V V k V V A V V V
PARAMETER RS-562/RS-232 TRANSMITTERS Output Voltage Swing Maximum Data Rate Input Logic Threshold Low Input Logic Threshold High Transmitter Pull-Up Input Current Output Leakage Current Output Resistance Output Short-Circuit Current RS-562/RS-232 RECEIVERS Input Voltage Range Input Threshold Low Input Threshold High Input Hysteresis Input Resistance Output Voltage Low Output Voltage High Output Leakage Current EN Input Logic Threshold Low EN Input Logic Threshold High POWER SUPPLY Operating Supply Voltage
VOUT = 12V, VCC = 0V or 3.6V to 5.5V, SHDN = GND VCC = V+ = V- = 0V, Transmitter Output = 2V VOUT = 0V
VCC -0.6 VCC -0.1
3
ISL8563E
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1F; Unless Otherwise Specified. Typicals are at TA = 25oC (Continued) TEST CONDITIONS SHDN = VCC SHDN = GND All Outputs Unloaded All Outputs loaded, RL = 3k Supply Current, Powerdown SHDN Input Leakage Current SHDN Input Logic Threshold Low SHDN Input Logic Threshold High VCC = 3.0V to 5.0V AC CHARACTERISTICS Transition Region Slew Rate Transmitter Propagation Delay VCC = 3.3V, RL = 3k to 7k, Measured From 3V to -3V or -3V to 3V, CL = 50pF to 2500pF Transmitter Input to Transmitter Output, CL = 1000pF, RL = 3k Receiver Input to Receiver Output, CL = 150pF Figure 1 Figure 1 Figure 2 Figure 2 tPHL - tPLH (Note 2) tPHL - tPLH (Note 3) Human Body Model IEC1000-4-2 Contact Discharge IEC1000-4-2 Air Gap Discharge All Other Pins NOTES: 2. Transmitter is measured at the transmitter zero crossing points. 3. Receiver is measured at the receiver 50 percent crossing points. Human Body Model tPHL (Note 2) tPLH (Note 2) tPHL (Note 3) tPLH (Note 3) tER tDR tET tDT 25 Full Full Full Full Full Full 25 25 25 25 25 25 25 25 4 1 1 0.3 0.3 125 160 17 600 100 100 15 8 15 3 30 3.5 3.5 1.0 1.0 500 500 V/s s s s s ns ns s ns ns ns kV kV kV kV TEMP (oC) Full 25 25 Full Full Full Full MIN 2.4 TYP 0.5 14 1 1 0.01 MAX 6.0 10 25 1.0 0.8 UNITS mA mA A A A V V
PARAMETER Supply Current
Receiver Propagation Delay Receiver Output Enable Time Receiver Output Disable Time Transmitter Output Enable Time Transmitter Output Disable Time Transmitter Skew Receiver Skew ESD PERFORMANCE RS-562 Pins (TOUT, RIN)
Test Waveforms
EN INPUT VCC 0V tER RECEIVER 0.5VCC OUTPUT C = 150pF to GND L RL = 1k to 0.5VCC VCC - 0.6V +0.4V VCC EN INPUT VOH RECEIVER OUTPUT VOH - 0.1V VOL VOL + 0.1V 0.5VCC CL = 150pF to GND RL = 1k to 0.5VCC TRANSMITTER OUTPUT V0V tDR V+ +3.7V 0V -3.7V CL = 50pF RL = 3k 0V CL = 50pF RL = 3k VCC 0V tDT -3.7V SHDN INPUT 0V tET +3.7V TRANSMITTER OUTPUT VCC
SHDN INPUT
FIGURE 1. RECEIVER OUTPUT ENABLE AND DISABLE TIMING
FIGURE 2. TRANSMITTER OUTPUT ENABLE AND DISABLE TIMING
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ISL8563E Detailed Description
The ISL8563E operates from a single +3V to +5.5V supply, guarantees a 250kbps minimum data rate, requires only four small external 0.1F capacitors, features low power consumption, and meets all ElA/TIA-562 and EIA/TIA-232 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers. (VCC = 0V). The receivers' Schmitt trigger input stage uses hysteresis (even in powerdown) to increase noise immunity and decrease errors due to slow input signal transitions. The ISL8563E inverting receivers disable only when EN is driven high. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral's protection diodes (see Figures 4 and 5).
VCC RXIN -25V VRIN +25V GND 5k RXOUT GND VROUT VCC
Charge-Pump
Intersil's new ISL8563E utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate 5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the 10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1F capacitors for the voltage doubler and inverter functions over the full VCC range. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings.
FIGURE 3. INVERTING RECEIVER CONNECTIONS
Powerdown Functionality
This 3V device requires a nominal supply current of 0.3mA during normal operation (not in powerdown mode). This is considerably less than the 5mA to 11mA current required by 5V devices. The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1A, because the onchip charge pump turns off (V+ collapses to VCC, Vcollapses to GND), the transmitter outputs three-state, and the transmitter input pull-ups disable. This micro-power mode makes the ISL8563E ideal for battery powered and portable applications.
Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-562/232 output levels. Coupled with the on-chip 5.5V supplies, these transmitters deliver true RS-562/232 levels over a wide range of single supply system voltages. All transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to 12V when disabled. All devices guarantee a 250kbps data rate (VOUT = 5V) for full load conditions (3k and 1000pF), VCC 3.0V, with one transmitter operating at full speed. Under more typical conditions of VCC 3.3V, RL = 3k, and CL = 250pF, one transmitter easily operates at 900kbps. Unused transmitter inputs may be left unconnected because they will be pulled to VCC by the on-chip pull-up resistors. Forcing the ISL8563E into power down disables the pull-up resistors to further minimize power.
Software Controlled (Manual) Powerdown
The ISL8563E, is forced into its low power, stand by state via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its powerdown state. Connect SHDN to VCC if the powerdown function isn't needed. Note that all the receiver outputs remain enabled during shutdown (see Table 2). For the lowest power consumption during powerdown, the receivers should also be disabled by driving the EN input high (see next section, and Figures 4 and 5). The time required to exit powerdown, and resume transmission is less than 30s.
Receiver ENABLE Control
The device also features an EN input to control the receiver outputs. Driving EN high disables all the receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down (VCC = GND) peripheral (see Figure 4). The enable input has no effect on transmitters.
Receivers
The ISL8563E contains standard inverting receivers that three-state via the EN control line. All the receivers convert RS-562/232 signals to CMOS output levels and accept inputs up to 25V while presenting the required 3k to 7k input impedance (see Figure 3) even if the power is off
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE SHDN INPUT L L H H EN INPUT L H L H TRANSMITTER OUTPUTS High-Z High-Z Active Active RECEIVER OUTPUTS Active High-Z Active High-Z MODE OF OPERATION Manual Powerdown Manual Powerdown w/Rcvr. Disabled Normal Operation Normal Operation w/Rcvr. Disabled
5
ISL8563E
VCC VCC VCC VOUT = VCC Rx POWERED DOWN UART GND CURRENT FLOW
Transmitter Outputs When Exiting Powerdown
Figure 6 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-562/232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3k in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V.
Tx
SHDN = GND
OLD RS-562/232 CHIP
5V/DIV.
SHDN T1
FIGURE 4. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL
VCC 2V/DIV. TRANSITION DETECTOR TO WAKE-UP LOGIC VCC ISL8563E T2 VCC = +3.3V C1 - C4 = 0.1F TIME (20s/DIV.) RX POWERED DOWN UART VOUT = HI-Z R2OUT TX T1IN T1OUT SHDN = GND, EN = VCC R2IN
FIGURE 6. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN
High Data Rates
The ISL8563E maintains the RS-232 5V minimum transmitter output voltages even at high data rates. Figure 7 details a transmitter loopback test circuit, and Figure 8 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 9 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver.
VCC 0.1F + + C1 C1+ C2 C2TIN ROUT EN VCC SHDN C2+ ISL8563E VVCC 400k TOUT RIN 5K 1000pF C4 + C1+ VCC V+ + C3
FIGURE 5. DISABLED RECEIVERS PREVENT POWER DRAIN
Capacitor Selection
The charge pumps operate with 0.1F (or greater) capacitors for 3.0V VCC 5.5V. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without increasing C1's value, however, do not increase C1 without also increasing C2, C3, and C4 to maintain the proper ratios (C1 to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor's equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
Power Supply Decoupling
In most circumstances a 0.1F bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC.
FIGURE 7. TRANSMITTER LOOPBACK TEST CIRCUIT
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ISL8563E 15kV ESD Protection
5V/DIV. T1IN
T1OUT
R1OUT VCC = +3.3V C1 - C4 = 0.1F 5s/DIV.
All pins on Intersil 3V interface devices include ESD protection structures, but the ISL8XXXE family incorporates advanced structures which allow the RS-562/232 pins (transmitter outputs and receiver inputs) to survive ESD events up to 15kV. These pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and don't interfere with RS-562/232 signals as large as 25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5k current limiting resistor, making the test less severe than the IEC-1000 test which utilizes a 330 limiting resistor. The HBM method determines an ICs ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-562/232 pins on "E" family devices can withstand HBM ESD events to 15kV.
FIGURE 8. LOOPBACK TEST AT 120kbps
5V/DIV. T1IN
T1OUT
IEC1000-4-2 Testing
R1OUT VCC = +3.3V C1 - C4 = 0.1F 2s/DIV.
FIGURE 9. LOOPBACK TEST AT 250kbps
Interconnection with 3V and 5V Logic
The ISL8563E directly interface with most 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections.
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES SYSTEM POWER-SUPPLY VOLTAGE (V) 3.3 VCC SUPPLY VOLTAGE (V) 3.3
The IEC 1000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-562/232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device's RS-562/232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-562/232 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The "E" device RS-562/232 pins withstand 15kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than 8kV. All "E" family devices survive 8kV contact discharges on the RS-562/232 pins.
COMPATIBILITY Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, or CD4000 CMOS.
5
5
5
3.3
7
ISL8563E Typical Performance Curves
6 TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ 4 20 2 1 TRANSMITTER AT 250kbps 1 TRANSMITTER AT 30kbps 0 -2 -4 -6 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) VOUT SLEW RATE (V/s)
VCC = 3.3V, TA = 25oC
25
15 -SLEW +SLEW 10
5 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF)
FIGURE 10. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE
45 40 250kbps SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 0 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) 20kbps 120kbps
FIGURE 11. SLEW RATE vs LOAD CAPACITANCE
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.5
NO LOAD ALL OUTPUTS STATIC
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
FIGURE 12. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA
FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE
Die Characteristics
DIE DIMENSIONS: 100 mils x 100 mils (2540m x 2540m) METALLIZATION: Type: Metal 1: AISi(1%) Thickness: Metal 1: 8kA Type: Metal 2: AISi (1%) Thickness: Metal 2: 10kA SUBSTRATE POTENTIAL (POWERED UP): Floating PASSIVATION: Type: Silox Thickness: 13kA TRANSISTOR COUNT: 338 PROCESS: Si Gate CMOS
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ISL8563E Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E18.3 (JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 21.47 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 22.35 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.845 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.880 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 18 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 18
2.93
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ISL8563E Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M18.3 (JEDEC MS-013-AB ISSUE C) 18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 11.35 7.40 MAX 2.65 0.30 0.51 0.32 11.75 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4469 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.4625 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 18 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 18 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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